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82571EB/82572EI Gigabit Ethernet Controller
Networking Silicon
Product Datasheet
Revision 1.2 August 2006
ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel product(s) referenced in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled platforms may require licenses from various entities, including Intel Corporation. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Intel(R) is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. Copyright (c) Intel Corporation, 2003 - 2006 *Other names and brands may be claimed as the property of others.
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Product Datasheet
82571EB/82572 Gigabit Ethernet Controller
Revision History
Date Oct 2002 Feb 2003 Revision 0.15 0.5 Initial Release Revised ballout, added package drawing, added visual pin descriptions, changed some ball names to "EXP" ball naming convention. * * Aug 2003 0.6 * * * * * * * Oct 2003 0.75 * * * * * * * May 2004 0.85 * January 2005 May 2005 Nov 2005 0.90 0.92 1.0 * * * * Updated power specifications. Changed names to "PE" naming convention Revised signal descriptions, pinout information tables, and ballout grid. Modified LAN disable ballout to cover A-0 (DEV_DIS_N) and B-0 (DEV_OFF_N). Removed integrated Baseboard Management Controller. Updated operating temperature Changed DEV_DIS_N pin (A Stepping) to RSVD_NC Corrected LED descriptions in signal descriptions in signal descriptions Added Absolute Maximum Ratings Added General Operating Conditions Added Power Specifications Added voltage Ramp and Sequencing Recommendations Added DC I/O Specifications Added Timing Specifications Edited Thermal Characteristics Section 4.4, Figure 2; Section 4.5.1.1;Section 4.5.1.2, Figure 5; Section 4.5.2, Figure 6; Section 5.1, Figure 7; Section 5.1, Figure 8; Section 5.4, Figure 9, ball T6 changed to PERST_N. Included 82572EI information Updated signal names Updated power numbers Corrected 1.1V Operating Range in Table 2 Changed document status to "Intel Confidential," updated power values, made minor corrections to text * Corrected pinlists * Pin A7 DEVICE_DIS_N has been moved to Reserved and No Connect Signals; this pin is now Reserved. Refer to 82571EB/82571EI Design Guide for guidance on proper connection. * Pin R4 LAN_PWR_GOOD has been moved to Reserved and No Connect Signals; this pin is now Reserved. Refer to 82571EB/82571EI Design Guide for guidance on proper connection. August 2006 1.2 * Corrected signal mames, minor text corrections Notes
March 2006
1.1
Product Datasheet
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82571EB/82572 Gigabit Ethernet Controller
Contents
1.0 Introduction..................................................................................................................................... 1 1.1 1.2 1.3 2.0 Document Scope................................................................................................................. 1 Reference Documents......................................................................................................... 2 Block Diagram.................................................................................................................... 3
Features of the 82571EB/82572EI Gigabit Ethernet Controller ................................................ 5 2.1 2.2 2.3 2.4 2.5 2.6 2.7 PCI Express Features.......................................................................................................... 5 MAC-Specific Features ...................................................................................................... 5 PHY Specific Features........................................................................................................ 6 Host Offloading Features.................................................................................................... 6 Manageability Features....................................................................................................... 7 Additional Device Features ................................................................................................ 7 Technology Features........................................................................................................... 8
3.0
Signal Descriptions.......................................................................................................................... 9 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 Signal Type Definitions...................................................................................................... 9 PCI Express Interface ......................................................................................................... 9 Power Management Signals ............................................................................................. 10 SMB and Fast Management Link Bus Signals ................................................................. 10 EEPROM and Serial FLASH Interface Signals ............................................................... 11 LED Signals...................................................................................................................... 11 Other Signals .................................................................................................................... 12 Crystal Signals .................................................................................................................. 12 PHY Analog Signals......................................................................................................... 12 Serializer / Deserializer Signals........................................................................................ 14 Test Interface Signals ....................................................................................................... 14 Power Supply Connections............................................................................................... 15 3.12.1 Digital and Analog Supplies .............................................................................. 15 3.12.2 Grounds, Reserved Pins and No Connects......................................................... 15
4.0
Voltage, Temperature, and Timing Specifications .................................................................... 17 4.1 4.2 Targeted Absolute Maximum Ratings.............................................................................. 17 Targeted Recommended Operating Conditions ............................................................... 18 4.2.1 General Operating Conditions............................................................................ 18 4.2.2 Voltage Ramps ................................................................................................... 19 4.2.3 Voltage Power Sequencing Options................................................................... 20 DC Specifications ............................................................................................................. 20 4.3.4 Power Specifications--82571EB ........................................................................ 21 4.3.5 Power Specifications--82572EI.......................................................................... 23 4.3.6 I/O Characteristics.............................................................................................. 25 Targeted AC Characteristics............................................................................................. 26 Targeted Timing Specifications........................................................................................ 28 4.5.1 PCI Express Interface......................................................................................... 28 4.5.2 EEPROM Interface ............................................................................................ 31 4.5.3 FLASH Interface ................................................................................................ 33
4.3
4.4 4.5
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Product Datasheet
82571EB/82572 Gigabit Ethernet Controller
5.0
Package and Pinout Information..................................................................................................35 5.1 5.2 5.3 5.4 Package Information..........................................................................................................35 Thermal Specification .......................................................................................................37 Pinout Information.............................................................................................................37 Visual Pin Assignments.....................................................................................................50
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82571EB/82572 Gigabit Ethernet Controller
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Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
1.0
Introduction
The Intel 82571EB Gigabit Ethernet Controller is a single, compact component with two fully integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) ports. The Intel 82572EI Gigabit Ethernet Controller is a single-port version of the controller in the same package. These devices use the PCI Express* architecture (Rev. 1.0a). The Intel 82571EB/82572EI enables dual- or single-port Gigabit Ethernet implementation in a very small area and can be used for server and workstation network designs with critical space constraints. The Intel 82571EB/82572EI provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). Ports also contain a Serializer-Deserializer (SERDES) to support 1000Base-SX/LX (optical fiber) and Gigabit backplane applications. In addition to managing MAC and PHY Ethernet layer functions, the controller manages PCI Express packet traffic across its transaction, link, and physical/logical layers. The Intel 82571EB/82572EI's on-board System Management Bus (SMB) ports enable network manageability implementations required by information technology personnel for remote control and alerting via the LAN. With SMB, management packets can be routed to or from a management processor. The SMB ports enable industry standards, such as Alert Standard Format (ASF) 2.0, to be implemented using the 82571EB/82572EI controller. In addition, on-chip ASF 2.0 circuitry provides alerting and remote control capabilities with standardized interfaces. Enhanced passthrough capabilities also allow system remote control over standardized interfaces. The 82571EB/82572EI Gigabit Ethernet Controller with PCI Express architecture is designed for high performance and low memory latency. The device is optimized to connect to a system Memory Control Hub (MCH) using four PCI Express lanes. Alternatively, the 82571EB/82572EI controller can connect to an I/O Control Hub (ICH6 & 7) that has a PCI Express interface. Wide internal data paths eliminate performance bottlenecks by efficiently handling large address and data words. Combining a parallel and pipe-lined logic architecture optimized for Gigabit Ethernet and independent transmit and receive queues, the 82571EB/82572EI controller efficiently handles packets with minimum latency. The 82571EB/82572EI controller includes advanced interrupt handling features. The 82571EB/82572EI uses efficient ring buffer descriptor data structures, with up to 64 packet descriptors cached on chip. A large 48 KByte per port on-chip packet buffer maintains superior performance. In addition, using hardware acceleration, the controller offloads tasks from the host, such as TCP/UDP/IP checksum calculations and TCP segmentation. The 82571EB/82572EI is packaged in a 17 mm X 17 mm, 256-ball grid array.
1.1
Document Scope
This document contains targeted datasheet specifications for the 82571EB/82572EI Gigabit Ethernet Controller, including signal descriptions, DC and AC parameters, packaging data, and pinout information.
Product Datasheet
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82571EB/82572 Gigabit Ethernet Controller
1.2
Reference Documents
This application assumes that the designer is acquainted with high-speed design and board layout techniques. The following documents provide additional information:
* * * * *
82571EB/82572EI Gigabit Ethernet Controller Design Guide, AP-447. Intel Corporation. Intel Ethernet Controllers Timing Device Selection Guide, AP-419. Intel Corporation. PCI Express Base Specification, Revision 1.0a. PCI Special Interest Group. PCI Express Card Electromechanical Specification, Revision 1.0a. PCI Special Interest Group. PCI Bus Power Management Interface Specification, Revision 1.1. PCI Special Interest Group. This version incorporates various IEEE standards previously published separately.
* IEEE Standard 802.3, 2000 Edition. Institute of Electrical and Electronics Engineers (IEEE).
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Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Host Arbiter
TX Switch DMA Engine PCIe Interface PCIe Core
Packet / Manageability Filter
TX MAC (10/100 / 1000 Mb) RX MAC (10/100 / 1000 Mb)
Link I /F
GMII / MII
MDIO Packet Buffer ASF Manageability RMON Statistics SM Bus
MDIO
EEPROM
Flash
Figure 1. 82571EB/82572EI Gigabit Ethernet Controller Block Diagram (Single Port Shown)
Block Diagram
Product Datasheet
1.3
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82571EB/82572 Gigabit Ethernet Controller
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Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
2.0
Features of the 82571EB/82572EI Gigabit Ethernet Controller
PCI Express Features
Features * Uses x4 PCI Express interface on MCH device Peak bandwidth 2 GB/s in each direction per PCI Express lane PCI Express Power Management * High bandwidth density per pin * * * * * Benefits Bus sharing not required Low latency path to memory Relieves congestion for IO devices Supports Gigabit Ethernet at full wire speed Compatible extensions to PCI power management and ACPI PE_WAKE_n available for wakeup event Less congested board routing
2.1
2.2
MAC-Specific Features
Features Optimized transmit and receive queues IEEE 802.3x compliant flow control support with software controllable pause times and threshold values Caches up to 64 packet descriptors (per queue) Separate transmit queue per port Programmable host memory receive buffers (256 Bytes to 16 KBytes) and cache line size (64 Bytes to 128 Bytes) Wide, pipelined internal data path architecture Dual 48 KByte configurable Transmit and Receive FIFO buffers Descriptor ring management hardware for transmit and receive Optimized descriptor fetching and write-back mechanisms Mechanism available for reducing interrupts generated by transmit and receive operations Supports transmission and reception of packets up to 9 kB * * * * * * * * * * * * Benefits Network packets handled without waiting or buffer overflow. Control over the transmissions of pause frames through software or hardware triggering Frame loss reduced from receive overruns Efficient use of PCI Express bandwidth Efficient packet prioritization Efficient use of PCI Express bandwidth Low latency data handling Superior DMA transfer rate performance No external FIFO memory requirements FIFO size adjustable to application Simple software programming model Efficient system memory and use of PCI Express bandwidth Maximizes system performance and throughput Enables jumbo frames
* *
Product Datasheet
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82571EB/82572 Gigabit Ethernet Controller
2.3
PHY Specific Features
Features Integrated PHY for 10/100/1000 Mbps operation IEEE 802.3ab Auto-Negotiation support IEEE 802.3ab PHY compliance and compatibility State-of-the-art DSP architecture implements digital adaptive equalization, echo cancellation, and cross-talk cancellation PHY cable correction and diagnostics * * * Low-Power Link-Up (LPLU) Smart Speed Smart Power-Down * * * * * * * * * Benefits Smaller footprint and lower power dissipation compared to multi-chip MAC and PHY solutions Automatic link configuration including speed, duplex, and flow control Robust operation over the installed base of Category-5 (CAT-5) twisted pair cabling Robust performance in noisy environments Tolerance of common electrical signal impairments Improved end-user troubleshooting Tolerance of common wiring faults Enables link in low-power mode Reacts to various link speeds
2.4
Host Offloading Features
Features Transmit and receive IP, TCP and UDP checksum offloading capabilities Transmit TCP segmentation * * * * * * Advanced packet filtering * * IEEE 802.1q VLAN support with VLAN tag insertion, stripping and packet filtering for up to 4096 VLAN tags Descriptor ring management hardware for transmit and receive 9 kB jumbo frame support * * * Benefits Lower CPU utilization Increased throughput and lower CPU utilization Large send offload feature (in Microsoft* Windows* XP) compatible Checksum and segmentation capability extended to new standard packet type 16 exact matched packets (unicast or multicast) 4096-bit hash filter for multicast frames Promiscuous (unicast and multicast) transfer mode support Optional filtering of invalid frames Ability to create multiple virtual LAN segments Optimized fetching and write-back mechanisms for efficient system memory and PCI bandwidth usage High throughput for large data transfers on networks supporting jumbo frames
IPv6 Offloading
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Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
2.5
Manageability Features
Features Manageability features: * * * Two SMBus ports one with Fast Management Link Capability Alerting Standards Format 1.0 and 2.0 Advanced Power Management (Wake on LAN) * * On-board microcontroller * * * Preboot eXecution Environment (PXE) Flash interface support (32-bit nd 64-bit) Compliance with PCI Power Management 1.1 and ACPI 2.0 register set compliant including: * * D0 and D3 power states Network Device Class Power Management Specification 1.1 * * * Easy system monitoring with industry standard consoles Remote network management capabilities through DMI 2.0 and SNMP software Packet recognition and wake-up for NIC and LOM applications without software configuration * PCI power management capability requirements for PC and embedded applications * Enables effective ASF 2.0 implementations Promotes customized designs Allows packets routing to and from either LAN port and a server management processor Supports serial text and keyboard redirection Supports remote floppy/CD Local Flash interface for PXE image * * * Alerting and control via standardized interfaces Network management flexibility Manageability data transfers up to 8 Mb/s peak rate Benefits
SNMP and RMON statistic counters SDG 3.0, WfM 3.0, and PC2001 compliance Wake on LAN support
2.6
Additional Device Features
Features * * 82571EB: Two complete Gigabit Ethernet connections in a single device * * * * Integrated SERDES Four activity and link indication outputs (per port) that directly drive LEDs Programmable LED functionality Internal PLL for clock generation can use a 25 MHz crystal * * * * Benefits Inherent dual port teaming ability High availability using one port for failover Higher throughput than single Gigabit Ethernet port Lower latency due to one electrical load on the bus Saves critical board space Reduced multi-port Gigabit Ethernet costs Supports backplane and fiber applications as well as copper-based Gigabit Link and activity indications (10, 100, and 1000 Mbps) on each port Software definable function (speed, link, and activity) and blinking allowing flexible LED implementations Lower component count and system cost
Product Datasheet
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82571EB/82572 Gigabit Ethernet Controller
Features JTAG (IEEE 1149.1) Test Access Port built in silicon Four software definable pins per port Provides loopback capabilities * * *
Benefits Simplified testing using boundary scan Additional flexibility for LEDs or other low speed I/O devices Validates silicon integrity
2.7
Technology Features
Features * 256-pin Flip-Chip Ball Grid Array (FC-BGA) package * Implemented in 90 nm CMOS process Operating temperature: 1000BASE-T, 0 C to 55 C (with thermal management) 1000BASE-T, 0 C to 70 C (with increased thermal management) 1000BASE-SX/LX (or SERDES backplane), 0C to 70 C Storage temperature 65 C to 140 C Typical targeted power dissipation: ~3.50 W @ D0 1000 Mbps ~0.78mW @ D3 100 Mbps (wakeup enabled) ~0.36mW @ D3 wakeup disabled * Minimizes impact of incorporating Gigabit instead of Fast Ethernet. * Simple thermal design Benefits 17 mm X 17 mm component occupies only 28% more board space than a single port device Offers lowest geometry to minimize power and size while maintaining Intel quality and reliability standards
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Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
3.0
Note:
Signal Descriptions
The targeted signal names are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design.
3.1
Signal Type Definitions
The signals of the 82571EB/82572EI controller are electrically defined as follows:
Name I O TS Input. Standard input only digital signal. Output. Standard output only digital signal. Tri-state. Bi-directional three-state digital input/output signal. Open Drain. Wired-OR with other agents. OD The signaling agent asserts the OD signal, but the signal is returned to the inactive state by a weak pullup resistor. The pull-up resistor may require two or three clock periods to fully restore the signal to the de-asserted state. Analog. PCI Express*, SERDES, or, PHY analog signal. Analog-Input. Standard input only analog signal. Analog-Output. Standard output only analog signal. Power. Power connection, voltage reference, or other reference connection. Definition
A A(I) A(O) P
3.2
PCI Express Interface
Symbol PERn[3:0] PERp[3:0] Type Name and Function High Speed Serial Receive Data. These signals connect to corresponding PETn and PETp signals on a system motherboard or a PCI Express connector. Series AC coupling capacitors are required at the transmitter end. The PCI Express differential inputs are clocked at 2.5 Gb/s. High Speed Serial Transmit Data. These signals connect to corresponding PERn and PERp signals on a system motherboard or a PCI Express connector. Series AC coupling capacitors are required at the 82571EB/82572EI controller end. The PCI Express differential outputs are clocked at 2.5 Gb/s. High Speed Serial Impedance Compensation. Connect the recommended resistor value across these balls. Refer to the 82571EB/82572EI Design Guide for the recommended value. 100 MHz Differential Clock for the PCI Express Interface. The reference clock is furnished by the system and has a 300 ppm frequency tolerance. PCI Express Reset. When the signal is low, all PCI Express functions are held in reset. When the signal is high, it denotes that main power is available to the 82571EB/82572EI controller and the reference clock is running. In systems with a PCI Express add-in card, this signal routes to the connector.
A(I)
PETn[3:0] PETp[3:0] PE_RCOMPp PE_RCOMPn PE_CLKp PE_CLKn
A(O)
P
I
PE_RSTn
I
Product Datasheet
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82571EB/82572EI Gigabit Ethernet Controller
3.3
Power Management Signals
Symbol AUX_PWR LAN0_DIS_N LAN1_DIS_N/ RSVD_B8 DEV_OFF_N Type I Name and Function Auxiliary Power Present. If the Auxiliary Power signal is high, then auxiliary power is present and the 82571EB/82572EI device should support the D3cold power state. LAN Disables 0 and 1. Disables individual Ethernet ports. State is latched upon a rising edge of PERST_N or a PCI Express reset event. This pin has an internal pull-up resistor. Device Off. Asynchronously disables Ethernet controller, including voltage regulator control outputs if selected in CTRL_EXT. This pin has an internal pull-up resistor. Wake. The 82571EB/82572EI device drives this signal low when it receives a wake-up event and either the PME Enable bit in the Power Management Control/Status Register or the Advanced Power Management Enable (APME) bit of the Wake-up Control Register (WUC) is 1b.
I
I
PE_WAKEn
OD
3.4
SMB and Fast Management Link Bus Signals
Symbol SMBCLK0/FLBMCK SMBCLK1 Type Name and Function SMB Clock. The SMB Clock signals are open drain signals for the serial SMB interface (Ports A and B). Alternatively, when SMB Port A is configured for a Fast Management Link Bus, SMB Clock A becomes the Fast Management Link Bus Master Clock. The Fast Management Link Bus can be clocked up to 6.5 MHz. SMB Data. The SMB Data signals are open drain signals for the serial SMB interface (Ports A and B). Alternatively, when SMB Port A is configured for a Fast Management Link Bus, SMB Data A becomes Fast Management Link Bus Master Data. SMB Alert. The SMB Alert signal is an open drain signal for serial SMB Port A. In ASF mode, this signal acts as a power good input. It acts as an alert input in 82559 compatible mode. Fast Management Link Bus Slave Data. When SMB Port A is configured for a Fast Management Link Bus, this signal becomes the serial data path for slave data from the 82571EB/82572EI controller. Fast Management Link Bus Interrupt Extension. Driven by the 82571EB/ 82572EI controller as a slave to alert the master to read data. Alternatively, it signals the master to extend the low phase of the clock.
I/O
SMBD0/FLBMD SMBD1 SMBALRT_N/ PCI_PWR_GOOD
I/O
I/O
FLBSD
O
FLBINTEX
O
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Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
3.5
EEPROM and Serial FLASH Interface Signals
Symbol EE_DI EE_DO EE_CS_N EE_SK FLSH_CE_N FLSH_SCK FLSH_SI FLSH_SO Type O I O O O O O I Name and Function EEPROM Data Input. The EEPROM Data Input pin is used for output to the SPI EEPROM memory device. EEPROM Data Output. The EEPROM Data Output pin is used for input from the SPI EEPROM memory device. The EE_DO includes an internal pull-up resistor. EEPROM Chip Select. The EEPROM Chip Select signal is used to enable the device. EEPROM Serial Clock. The EEPROM Shift Clock provides the clock rate for the SPI EEPROM interface, which is approximately 2 MHz. FLASH Chip Enable Output. Used to enable FLASH device. FLASH Serial Clock Output. FLASH Serial Data Input. This pin is an output to the memory device. FLASH Serial Data Output. This pin is an input from the memory device.
3.6
LED Signals
Symbol LED0_0 LED0_1 LED0_2 LED0_3 LED1_0/ RSVD_P8 LED1_1/ RSVD_R8 LED1_2/ RSVD_T8 LED1_3/ RSVD_P9 Type O O O O O O O O Name and Function LED0_0. Programmable LED output for Port A. As the Link LED, it indicates link connectivity on Port A. LED0_1. Programmable LED output for Port A. As the Activity LED, it flashes to indicate receive activity on Port A for packets destined for this node. LED0_2. Programmable LED output for Port A. As the Link 100 LED, it indicates link at 100 Mbps for Port A. LED0_3. Programmable LED output for Port A. As the Link 1000 LED, it indicates link at 1000 Mbps for Port A. LEDB0_N. Programmable LED output for Port B. As the Link LED, it indicates link connectivity on Port B. (82571 EB only.) LED1_1. Programmable LED output for Port B. As the Activity LED, it flashes to indicate receive activity on Port B for packets destined for this node. (82571 EB only.) LED1_2. Programmable LED output for Port B. As the Link 100 LED, it indicates link at 100 Mbps for Port B. (82571 EB only.) LED1_3. Programmable LED output for Port B. As the Link 1000 LED, it indicates link at 1000 Mbps for Port B. (82571 EB only.)
Product Datasheet
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82571EB/82572EI Gigabit Ethernet Controller
3.7
Other Signals
Symbol SDP0_1 SDP0_2 SDP0_3 SDP0_4 SDP1_1/RSVD_P6 SDP1_2/RSVD_B6 SDP1_3/RSVD_C6 SDP1_4/RSVD_R6 Type Name and Function
TS
Software Defined Pin. The Software Defined Pins are programmable with respect to input and output capability. SDP0_3 and SDP1_3 may optionally be configured as interrupt inputs. SDP signals default to inputs upon power-up, but may be configured differently by the EEPROM.
3.8
Crystal Signals
Symbol Type Name and Function Crystal One. The Crystal One pin is a 25 MHz input signal. It should be connected to a parallel resonant crystal with a frequency tolerance of 30 ppm or better. The other end of the crystal should be connected to XTAL2. Optionally, an oscillator can be connected to XTAL 1. See the design guide for more information.. Crystal Two. Crystal Two is the output of an internal oscillator circuit used to drive a crystal into oscillation.
XTAL1
I
XTAL2
O
3.9
PHY Analog Signals
Port 0
Symbol RBIAS0p RBIAS0n Type Name and Function Bias Resistors. These are the reference connections for the Media Dependent Interface. The recommended resistor value should be connected across the positive/negative pair, even if the MDI interface is not used. Refer to the 82571EB/82572EI Design Guide for the recommended value. Media Dependent Interface [0].
1000BASE-T: In MDI configuration, these correspond to BI_DA+/-, and in MDI-X
P
MDI_PLUS0_0 MDI_MINUS0_0
configuration, they correspond to BI_DB+/-. A
100BASE-TX: In MDI configuration, these are used for the transmit pair, and in MDI-X
configuration, they are used for the receive pair. 10BASE-T: In MDI configuration, they are used for the transmit pair, and in MDI-X configuration, used for the receive pair.
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Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Symbol
Type Media Dependent Interface [1].
Name and Function
MDI_PLUS0_1 MDI_MINUS0_1
1000BASE-T: In MDI configuration, these correspond to BI_DB+/-, and in MDI-X configuration, they correspond to BI_DA+/-.
A
100BASE-TX: In MDI configuration, they are used for the receive pair, and in MDI-X configuration, they are used for the transit pair.
10BASE-T: In MDI configuration, they are used for the receive pair, and in MDI-X configuration, they are used for the transit pair. Media Dependent Interface [2]. MDI_PLUS0_2 MDI_MINUS0_2 A
1000BASE-T: In MDI configuration, these correspond to BI_DC+/-, and in MDI-X configuration, they correspond to BI_DD+/-. 100BASE-TX: Unused.
10BASE-T: Unused. Media Dependent Interface [3]. MDI_PLUS0_3 MDI_MINUS0_3 A
1000BASE-T: In MDI configuration, these correspond to BI_DD+/-, and in MDI-X configuration, they correspond to BI_DC+/-. 100BASE-TX: Unused.
10BASE-T: Unused.
Port 1 (82571EB Only)
Symbol RBIAS1p/ RSVD_M14 RBIAS1n/ RSVD_N14 Type Name and Function Bias Resistors. These are the reference connections for the Media Dependent Interface. The recommended resistor value should be connected across the positive/negative pair, even if the MDI interface is not used. Refer to the 82571EB/82572EI Design Guide for the recommended value. Media Dependent Interface [0]. MDI_PLUS1_0/ RSVD_T14 MDI_MINUS1_0/ RSVD_R14
1000BASE-T: In MDI configuration, these correspond to BI_DA+/-, and in MDI-X
P
configuration, they correspond to BI_DB+/-. A
100BASE-TX: In MDI configuration, they are used for the transmit pair, and in MDI-X configuration, they are used for the receive pair.
10BASE-T: In MDI configuration, they are used for the transmit pair, and in MDI-X configuration, they are used for the receive pair. Media Dependent Interface [1]. MDI_PLUS1_1/ RSVD_T15 MDI_MINUS1_1/ RSVD_R15
1000BASE-T: In MDI configuration, these correspond to BI_DB+/-, and in MDI-X
configuration, they correspond to BI_DA+/-. A
100BASE-TX: In MDI configuration, they are used for the receive pair, and in MDI-X configuration, they are used for the transit pair.
10BASE-T: In MDI configuration, they are used for the receive pair, and in MDI-X configuration, they are used for the transit pair. Media Dependent Interface [2]. MDI_PLUS1_2/ RSVD_P16 MDI_MINUS1_2/ RSVD_P15 A
1000BASE-T: In MDI configuration, these correspond to BI_DC+/-, and in MDI-X configuration, they correspond to BI_DD+/-. 100BASE-TX: Unused.
10BASE-T: Unused. Media Dependent Interface [3]. MDI_PLUS1_3/ RSVD_N16 MDI_MINUS1_3/ RSVD_N15 A
1000BASE-T: In MDI configuration, these correspond to BI_DD+/-, and in MDI-X configuration, they correspond to BI_DC+/-. 100BASE-TX: Unused.
10BASE-T: Unused.
Product Datasheet
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82571EB/82572EI Gigabit Ethernet Controller
3.10
Serializer / Deserializer Signals
Symbol SRDSI_0_PLUS SRDSI_0_MINUS SRDSI_1_PLUS/ RSVD_M16 SRDSI_1_MINUS/ RSVD_L16 A(I) Type Name and Function SERDES Receive Pairs. Signals SRDSI_0_PLUS and SRDSI_0_MINUS make the differential receive pair for the 1.25 GHz serial interface for Port 0. For serializer/ deserializer operation, the inputs should be coupled to ECL voltage levels. Signals SRDSI_1_PLUS and SRDSI_1_MINUS make the differential receive pair for the 1.25 GHz serial interface for Port 1. For serializer/deserializer operation, the inputs should be coupled to ECL voltage levels. If the SERDES interface is not used, these pins should not be connected. SRDSO_0_PLUS SRDSO_0_MINUS SRDSO_1_PLUS/ RSVD_K15 SRDSO_1_MINUS /RSVD_L15 SRDSA_SIG_DET SRDSB_SIG_DET/ RSVD_C4 SRDS_RCOMPp SRDS_RCOMPn I A(O) SERDES Transmit Pairs. Signals SRDSO_0_PLUS and SRDSO_0_MINUS make the differential transmit pair for the 1.25 GHz serial interface for Port 0. For serializer/ deserializer operation, the outputs drive the LVPECL voltage levels. Signals SRDSO_1_PLUS and SRDSO_1_MINUS make the differential transmit pair for the 1.25 GHz serial interface for Port 1. For serializer/deserializer operation, the outputs drive the LVPECL voltage levels. If the SERDES interface is not used, these pins should not be connected. Signal Detects. These pins (SRDSA_SIG_DET for Port 0; SRDSB_SIG_DET for Port 1) indicate whether the SERDES signals (connected to the 1.25 GHz serial interface) have been detected by the optical transceivers. If the SERDES interface is not used, the SIG_DET inputs can be left unconnected. SERDES Impedance Compensation. Connect the recommended resistor value across these balls, even if not using the SERDES interface. Refer to the 82571EB/82572EI Design Guide for the recommended value.
A
3.11
Test Interface Signals
Symbol JTCK JTDI JTDO JTMS Type I I O I Name and Function JTAG Test Access Port Clock. JTAG Test Access Port Test Data In. JTAG Test Access Port Test Data Out. JTAG Test Access Port Mode Select.
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Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Symbol IEEE_TEST0p IEEE_TEST0n IEEE_TEST1p/ RSVD_R13 IEEE_TEST1n/ RSVD_T13 THERM_Dp THERM_Dn TEST_EN
Type
Name and Function
O
IEEE Analog Test Pins. Differential outputs providing reference clocks for IEEE PHY conformance verification. For prototype testing, connect each pair to two-pin headers. For production systems, leave pins unconnected.
O I
Thermal Diode Reference. Can be used to measure the Si temperature. Factory Test Pin. Attach a 1 K pull-down resistor to ground for normal operation.
3.12
3.12.1
Power Supply Connections
Digital and Analog Supplies
Symbol VCC33 VCC18 VCC11
Type P P P
Name and Function 3.3V Digital Power Supply. For I/O circuits. 1.8V Analog Power Supply. For PHY analog, PHY I/O, PCI Express analog, and Phase Lock Loop circuits, Connect all 1.8V pins to a single power supply. 1.1V Digital Power Supply. For core digital, PHY digital, PCI Express digital and clock circuits, connect all 1.1V pins to a single power supply.
3.12.2
Grounds, Reserved Pins and No Connects
Symbol VSSA VSS Type P P Name and Function Analog Ground. Connects to PHY analog circuits. Connect directly to analog ground. Digital Ground. Connects to core and digital I/O. Connect to GND. Reserved Pin. These pins are reserved by Intel and may have factory test functions. For normal operation, do not connect any circuitry to these pins (allow them to "float"). Some special configurations may require pull-up or pull-down resistors on these pins. Please refer to the 82571EB/82572EI design guide for more information. No Connect. This pin is not connected internally.
RSVD_ pin#
P
NC_pin#
P
Product Datasheet
15
82571EB/82572EI Gigabit Ethernet Controller
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Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
4.0
4.1
Table 1.
Voltage, Temperature, and Timing Specifications
Targeted Absolute Maximum Ratings
Absolute Maximum Ratingsa
Symbol VCC(3.3) VCC(1.8) VCC(1.1) Parameter DC supply voltage on 3.3V pins with respect to VSS DC supply voltage on 1.8V pins with respect to VSSb DC supply voltage on 1.1V pins with respect to VSSb 3.3V I/O Voltage VI / VO IO Tstorage 1.8V I/O Voltage 1.1V I/O Voltage DC output current Storage temperature range ESD per MIL_STD-883 Test Method 3015, Specification 2001V Latchup Over/Undershoot: 150 mA, 125 C
a.
Min VSS - 0.5 VSS - 0.3 VSS - 0.2 VSS - 0.5 VSS - 0.3 VSS - 0.2 N/A -65 N/A
Max 4.6 2.5 1.7 4.6 2.5 1.7 30 140 VDD overstress: VDD(3.3) * (7.2 V)
Unit V V V
V mA C V
Maximum ratings are referenced to ground (VSS). Permanent device damage is likely to occur if the ratings in this table are exceeded for an indefinite duration. These values should not be used as the limits for normal device operations. b. During normal device power up and power down, the 1.8V and 1.1V supplies must not ramp before the 3.3V supply.
Product Datasheet
17
82571EB/82572EI Gigabit Ethernet Controller
4.2
4.2.1
Table 2.
Targeted Recommended Operating Conditions
General Operating Conditions
Recommended Operating Conditions a
Symbol VCC(3.3) VCC(1.8) VCC(1.1) tR / tF Ta TJ
a.
Parameter DC supply voltage on 3.3V pins DC supply voltage on 1.8V pins
b, c
Min 3.0 1.71 1.045 0 0 N/A
Max 3.6 1.89 1.155 200 55
d
Unit V V V ns C C
DC supply voltage on 1.1V pins Input rise/fall time (normal input) Operating temperature range (ambient) Junction temperature
110
Sustained operation of the device at conditions exceeding these values, even if they are within the absolute maximum rating limits, might result in permanent damage. Device functionality to stated DC and AC limits is not guaranteed, if conditions exceed recommended operating conditions. b. See Section 4.2.2 for voltage ramp and sequencing recommendations. c. Operation with internal voltage regulator control of PNP pass transistor may exceed this range due to 82571EB process skew tracking. d. 1000BASE-T designs require thermal management (heatsink and/or forced air flow) to achieve 0 to 55 C operation. Increased thermal management can increase this temperature range to 0 to 70 C. Applications using the SERDES interface are rated for 0 to 70 C without thermal management.
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Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
4.2.2
Table 3.
Voltage Ramps
3.3V Supply Voltage Ramp
Parameter Rise Time Monotonicity Slope Operational Range Ripple Overshoot Settling Time Overshoot Description Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any time between 10% to 90% Voltage range for normal operating conditions Maximum voltage ripple at a bandwidth equal to 50 MHz Overshoot time upon rampb Maximum voltage allowedb Min 0.1 N/A 24 3 N/A N/A N/A Max 100a 0 28000 3.6 70 0.05 100 Unit ms mV mV/ms V mVpeak-peak ms mV
a. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less. b. Excessive overshoot can affect long term reliability.
Table 4.
1.8V Supply Voltage Ramp
Parameter Rise Time Monotonicity Slope Operational Range Ripple Overshoot SettlingTime Overshoot Description Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any time between 10% to 90% Voltage range for normal operating conditions Maximum voltage ripple at a bandwidth equal to 1 MHz Overshoot time upon rampb Maximum voltage allowedb Min 0.1 N/A 14 1.71 N/A N/A N/A Max 100a 0 60000 1.89 40 0.1 100 Unit ms mV mV/ms V mVpeak-peak ms mV
a. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less. b. Excessive overshoot can affect long term reliability.
Table 5.
1.1V Supply Voltage Ramp
Parameter Rise Time Monotonicity Slope Operational Range Description Time from 10% to 90% mark Voltage dip allowed in ramp Ramp rate at any time between 10% to 90% Voltage range for normal operating conditions Min 0.1 N/A 7.6 1.045 Max 100 0 33600 1.155
a
Unit ms mV mV/ms V
Product Datasheet
19
82571EB/82572EI Gigabit Ethernet Controller
Table 5.
1.1V Supply Voltage Ramp
Ripple Overshoot SettlingTime Overshoot Maximum voltage ripple at a bandwidth equal to 1 MHz Overshoot time upon rampb Maximum voltage allowedb N/A N/A N/A 40 0.05 100 mVpeak-peak ms mV
a. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less. b. Excessive overshoot can affect long term reliability.
4.2.3
Voltage Power Sequencing Options
To meet 375 mA inrush current requirements (not including external capacitors) the ramp time should be 5 ms -100 ms on all power rails. For faster ramps (100 us - 5 ms), expect higher inrush current due to the high charging current of the decoupling capacitors of 3.3V, 1.8V and 1.1V rails.
4.3
Table 6.
DC Specifications
DC Characteristics
Symbol VCC(3.3) VCC(1.8) VCC(1.1) Parameter DC supply voltage on 3.3V pins DC supply voltage on 1.8V pins DC supply voltage on 1.1V pins Condition Min 3.00 1.71 1.045 Typ 3.30 1.80 1.100 Max 3.60 1.89 1.155 Units V V V
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Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
4.3.4
Power Specifications--82571EB
Table 7.
D0a--Active Link
D0a--Active Link @10 Mbps Typ Icc (mA)a 3.3V 1.8V 1.1V Total Device Power
a.
@100 Mbps Typ Icc (mA)a 26 399 456
@ 1000 Mbps (copper) Typ Icc (mA)a 26 893 1022 Max Icc (mA)a 34 913 1520
@ 1000 Mbps (SERDES) Typ Icc (mA)a 42 254 529 Max Icc (mA)b 46 282 1002
26 350 370
1.12W
1.31W
2.82W
3.43W
1.18W
1.76W
Typical conditions: operating temperature (TA) = 25 C, nominal voltages and continuous network traffic at link speed at full duplex. b. Maximum conditions: maximum operating temperature (TJ) values, typical voltage values and continuous network traffic at link speed at full duplex.
Product Datasheet
21
82571EB/82572EI Gigabit Ethernet Controller
Table 8.
D0a--Idle Link L0s Only
D0a--Idle Link L0s Only Unplugged--no link @10Mbps @100Mbps @1000Mbps (copper)
Typ Icc (mA)a 3.3V 1.8V 1.1V Total Device Power
a.
26 130 332
26 123 334
26 306 414
26 837 839
0.69W
0.67W
1.10W
2.52W
Typical conditions: room temperature (TA)=25C, nominal voltages and idle network (no traffic) at full duplex
Table 9.
D3cold
D3cold - wake-up enabled @10 Mbps Typ Icc (mA)a, b 3.3V 1.8V 1.1V Total Device Power
a.
@100 Mbps Typ Icc (mA)a, b 26 243 236 0.78W
D3coldwake disabled (no link) Typ Icc (mA)a b 26 76 123 0.36W
26 74 133 0.37W
D3 Cold activated on a Windows Server 2003 OS--using Hbernate mode b. L0s enable, L1 disabled
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Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Table 10. D(r) Unintialized
D(r) Uninitialized Disabled through LAN_DIS_N Disabled through DEV_OFF_N Typ Icc (mA) Typ Icc (mA) 3.3V 1.8V 1.1V Total Device Power 26 63 130 0.34W 26 68 83 0.30W
4.3.5
Power Specifications--82572EI
Table 11. D0a--Active Link
D0a--Active Link @10 Mbps Typ Icc (mA)a 3.3V 1.8V 1.1V Total Device Power
a.
@100 Mbps Typ Icc (mA)a 26 211 232
@ 1000 Mbps (copper) Typ Icc (mA)a 26 484 494 Max Icc (mA)a 34 502 1023
26 210 291
0.78W
0.72W
1.50W
2.14W
Typical conditions: operating temperature (TA) = 25 C, nominal voltages and continuous network traffic at link speed at full duplex.
Product Datasheet
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82571EB/82572EI Gigabit Ethernet Controller
Table 12. D0a--Idle Link
D0a--Idle Link L0s Only Unplugged--no link @10Mbps @100Mbps @1000Mbps (copper)
Typ Icc (mA)a 3.3V 1.8V 1.1V Total Device Powerb
a.
26 111 176
26 102 179
26 199 218
26 425 839
0.48W
0.47W
0.68W
1.77W
Typical conditions: room temperature (TA)=25C, nominal voltages and idle network (no traffic) at full duplex b. LOs enabled; L1 disabled
Table 13. D3cold
D3cold - wake-up enabled @10 Mbps Typ Icc (mA)a, b 3.3V 1.8V 1.1V Total Device Power 26 77 120 0.36W @100 Mbps Typ Icc (mA)a, b 26 173 163 0.58W
D3cold-wake disabled; unplugged, no link
Typ Icc (mA)a b 26 84 110 0.36W
a. D3 Cold activated on a Windows Server 2003 OS--using Hbernate mode b. LOs enabled, L1 disabled
Table 14. D(r) Unintialized
D(r) Uninitialized Disabled through LAN_DIS_N Disabled through DEV_OFF_N Typ Icc (mA) Typ Icc (mA) 3.3V 26 26
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Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Table 14. D(r) Unintialized
D(r) Uninitialized Disabled through LAN_DIS_N Disabled through DEV_OFF_N Typ Icc (mA) Typ Icc (mA) 1.8V 1.1V Total Device Power 60 114 0.32W 68 83 0.30W
4.3.6
I/O Characteristics
Table 15. I/O Characteristicsa
Symbol VIH VIL IIN Parameter Input high voltage Input low voltage Input current VIN = VDD(3.3) or VSS IOH = -16 mA VOH Output high voltage VCC = Min IOH = -100 A VCC = Min IOL = 16 mA VOL Output low voltage VCC = Min IOL = 100 A VCC = Min IOZ CINb PU Off-state output leakage current Input capacitance Internal pull-up VO = VCC or VSS Condition Min 2.0 -0.5 -15 2.4 VCC - 0.02 N/A N/A -10 N/A 2.6 Typ N/A N/A N/A N/A N/A N/A N/A N/A 2.5 N/A Max VCC(3.3) + 0.5 0.8 15 N/A V N/A 0.4 V 0.2 10 N/A 5.5 A pF k Units V V A
a. The input buffer also has hysteresis > 160 mV. b. Cin= 2.5 pF(maximum input capacitance), Cout = 16 pF (characterized max output load capacitance per 160 MHz).
Product Datasheet
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82571EB/82572EI Gigabit Ethernet Controller
4.4
Targeted AC Characteristics
Table 16. 25 MHz Clock Input Requirements
Symbol f0 df0 Dc tr tf Jptp Cin T Aptp Vcm
a.
Parameter Frequency Frequency Variation Duty Cycle Rise Time Fall Time Clock Jitter (peak-to-peak) Input Capacitance Operating Temperature Input clock amplitude (peak-to-peak) Clock common mode
a
Min N/A -50 40 N/A N/A N/A N/A N/A 1.0 N/A
Typ 25.000 N/A N/A N/A N/A N/A 20 N/A 1.2 0.6
Max N/A +50 60 5 5 250 N/A 70 1.3 N/A
5
Unit MHz ppm % ns ns ps pF C V V
Clock jitter is defined according to the recommendations of part 40.6.1.2.5 IEEE 1000Base-T Standard (at least 10 clock edges, filtered by HPF with cut off frequency of 5000 Hz).
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Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Table 17. Reference Crystal Specification Requirements
Specification Vibrational Mode Nominal Frequency Value Fundamental 25.000 MHz at 25 C * 30 ppm recommended Frequency Tolerance * 50 ppm across the entire operating temperature range (required by IEEE specifications) +/- 30 ppm at 0 C to 70 C Parallel 20 pF to 24 pF 6 pF maximum 50 maximum 0.5 mW maximum +/- 5.0 ppm per year maximum 500 minimum at DC 100 V 4 pF 27 pF 0.1
Temperature Stability Calibration Mode Load Capacitance Shunt Capacitance Series Resistance, Rs Drive Level Aging Insulation Resistance Board Capacitance External Capacitors Board Resistance
Table 18. Link Interface Clock Requirements
Symbol fGTXa
a.
Parameter GTX_CLK frequency
Min N/A
Typ 125
Max N/A
Unit MHz
GTX_CLK is used externally for test purposes only.
Table 19. EEPROM Interface Clock Requirements
Symbol fSK Parameter SPI EEPROM Clock Min N/A Typ 2 Max 2.1 Unit MHz
Table 20. AC Test Loads for General Output Pins
Symbol CL Parameter Capacitance of test load Min N/A Typ 16 Max N/A Unit pF
Product Datasheet
27
82571EB/82572EI Gigabit Ethernet Controller
CL
Figure 2. AC Test Loads for General Output Pins
4.5
Note:
Targeted Timing Specifications
Timing specifications are preliminary and subject to change. Verify with your local Intel sales office that you have the latest information before finalizing a design.
4.5.1
4.5.1.1
PCI Express Interface
Differential Transmitter (TX) Output Specifications
Table 21. Differential Transmitter (TX) Output Specifications
Symbol UI VTX-DIFFp-p Parameter Unit Interval Differential Peak to Peak Output Voltage De-Emphasized Differential Output Voltage (Ratio) Minimum TX Eye Width D+/D- TX Output Rise/Fall Time RMS AC Peak Common Mode Output Voltage Absolute Delta of DC Common Mode Voltage between D+ and DElectrical Idle Differential Peak Output Voltage Min 399.88 0.800 Typ 400 N/A Max 400.12 1.2 Units ps V
VTX-DE-RATIO
-3.0
-3.5
-4.0
dB
TTX-EYE TTX-RISE, TTX-FALL VTX-CM-ACp
0.70 0.125
N/A N/A
N/A N/A
UI UI
N/A
N/A
20
mV
VTX-CM-DC-LINEDELTA
0
N/A
25
mV
VTX-IDLE-DIFFp
0
N/A
20
mV
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Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Table 21. Differential Transmitter (TX) Output Specifications
Symbol Parameter The amount of voltage change allowed during Receiver Detectoin Differential Return Loss Common Mode Return Loss DC Differential TX Impedance Lane-toLane Output Skew Min Typ Max Units
VTX-RCV-DETECT
N/A
N/A
600
mV
RLTX-DIFF RLTX-CM ZTX-DIFF-DC LTX-SKEW
12 6 80 N/A
N/A N/A 100 N/A
N/A N/A 120 500 + 2 UI
dB dB
ps
VTX-DIFF = 0 mV (D+ D- Crossing Point)
[Transition Bit] VTX-DIFFp-p-MIN = 800 mV
VTX-DIFF = 0 mV (D+ D- Crossing Point)
[De-emphasized Bit] 566 mV (3 dB) >= VTX-DIFFp-p-MIN >= 505 mV (4 dB)
0.7 UI = UI - 0.3 UI(JTX-TOTAL-MAX) [Transition Bit] VTX-DIFFp-p-MIN = 800 mV
Figure 3. PCI Express Transmitter Eye Diagram
Product Datasheet
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82571EB/82572EI Gigabit Ethernet Controller
D+ Package Pin C = CTX
TX Silicon + Package
C = CTX D- Package Pin R = 50 R = 50
Figure 4. PCI Express Transmitter Test Load
4.5.1.2
Differential Receiver (RX) Input Specifications
Table 22. Differential Receiver (RX) Output Specifications
Symbol UI VRX-DIFFp-p RTX-EYE VRX-CM-ACp RLRX-DIFF RLRX-CM ZRX-DIFF-DC LRX-SKEW Parameter Unit Interval Differential Peak to Peak Output Voltage Minimum RX Eye Width AC Peak Common Mode Input Voltage Differential Return Loss Common Mode Return Loss DC Differential Input Impedance Total Skew Min 399.88 0.175 Typ 400 N/A Max 400.12 1.2 Units ps V
0.4
N/A
N/A
UI
N/A
N/A
150
mV
15 6 80 N/A
N/A N/A 100 N/A
N/A N/A 120 20
dB dB
ns
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Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
VRX-DIFF = 0 mV (D+ D- Crossing Point)
VRX-DIFF = 0 mV (D+ D- Crossing Point)
VRX-DIFFp-p-MIN > 175 mV
0.4 UI = TRX-EYE-MIN
Figure 5. PCI Express Receiver Eye Diagram
4.5.2
EEPROM Interface
Table 23. EEPROM Interface Time Specifications
Symbol tSCK tRI tFI tWH tWH tCS tCSS tCSH tSU tH tV tHO tDIS tWC
a. 50% duty cycle.
Parameter SCK clock frequency Input rise time Input fall time SCK high timea SCK low time CS high time CS setup time CS hold time Data-in setup time Data-in hold time Output Valid Output hold time Output disable time Write cycle time
a
Min 0 N/A N/A 200 200 250 250 250 50 50 0 0 N/A N/A
Typ 2 2.5 ns 2.5 ns 250 250 N/A N/A N/A N/A N/A N/A N/A N/A N/A
Max 2.1 2 2 N/A N/A N/A N/A N/A N/A N/A 200 N/A 250 10
Units MHz s s ns ns ns ns ns ns ns ns ns ns ms
Product Datasheet
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82571EB/82572EI Gigabit Ethernet Controller
tCS VIH CS VIL VIH SCK VIL tSU VIH SI VIL tV VIH SO VIL Hi-Z tHO tDIO Hi-Z VALID IN tH tCSS tWL tWH
tCSH
Figure 6. EEPROM Interface Time Diagram
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82571EB/82572EI Gigabit Ethernet Controller
4.5.3
FLASH Interface
Table 24. FLASH Interface Time Specifications
Symbol tSCK tRI tFI tWH tWH tCS tCSS tCSH tSU tH tV tHO tDIS tEC
a. 50% duty cycle.
Parameter SCK clock frequency Input rise time Input fall time SCK high time SCK low time CS high time CS setup time CS hold time Data-in setup time Data-in hold time Output Valid Output hold time Output disable time Erase cycle time per sector
a
Min 0 N/A N/A 20 20 25 25 250 5 5 0 0 N/A N/A
Typ 15.625 2.5 ns 2.5 ns 32 32 N/A N/A N/A N/A N/A N/A N/A N/A 60
Max 20 20 20 N/A N/A N/A N/A N/A N/A N/A 20 N/A 100 100
Units MHz ns ns ns ns ns ns ns ns ns ns ns ns s
a
tCS VIH CS VIL tcss VIH Sck VIL tSU VIH SI VIL tv SO VOH VOL HI-Z tHO tDIS HI-Z VALID IN tH tWH tWL
tCSH
Figure 7. FLASH Interface Time Diagram
Product Datasheet
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82571EB/82572EI Gigabit Ethernet Controller
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82571EB/82572EI Gigabit Ethernet Controller
5.0
Package and Pinout Information
This section describes the 82571EB/82572EI device physical characteristics. The pin number-tosignal mapping is indicated beginning with Table 25. Note: The targeted signal names are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design.
5.1
Package Information
The 82571EB/82572EI device is a 256-lead flip-chip ball grid array (FC-BGA) measuring 17 mm by 17 mm. The nominal ball pitch is 1 mm. See Figure 9.
Detail Area
0.43 mm Solder Resist Opening
0.62 mm Metal Diameter
Figure 8. 82571EB/82572EI Controller FC-BGA Package Ball Pad Dimensions
Product Datasheet
33
82571EB/82572EI Gigabit Ethernet Controller
Figure 9. 82571EB/82572EI Mechanical Specifications
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Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
5.2
Thermal Specification
The 82571EB/82572EI device is specified for operation when the ambient temperature (TA) is within the range of 0 C to 55 C. For more information about the thermal characteristics of the device, including operation outside of this range, please refer to the 82571EB/82572EB Thermal Application Note, AP-490
5.3
Pinout Information
Signal names apply to both the 82571EB and the 82572EI unless there is a "/", which indicates that the the first name is for the 82571EB and the second name is for the 82572EI. Table 25. PCI Express Signals
Signal PERn0 PERp0 PERn1 PERp1 PERn2 PERp2 PE_CLKn Pin R2 T2 M2 N2 E1 F1 J2 Signal PERn3 PERp3 PETn0 PETp0 PETn1 PETp1 PE_CLKp Pin B1 C1 P1 R1 L1 M1 K2 Signal PETn2 PETp2 PETn3 PETp3 PE_RCOMPn PE_RCOMPp PE_RSTn Pin D2 E2 A2 B2 G2 H2 T6
Table 26. Power Management Signals
Signal LAN0_DIS_N LAN1_DIS_N/ RSVD_B8 DEV_OFF_N Pin B7 B8 T3 Signal PE_WAKEn AUX_PWR Pin P11 C8
Table 27.
SMB/Fast Management Link Bus Signals
Signal SMBCLK0/ FLBMCK SMBD0/FLBMD Pin T12 R12 Signal SMBCLK1 SMBD1 Pin P13 P12 Signal SMBALRT_N/ PCI_PWR_GOOD FLBSD FLBINTEX Pin R11 P7 R7
Product Datasheet
35
82571EB/82572EI Gigabit Ethernet Controller
Table 28. EEPROM and Serial FLASH Interface Signals
Signal EE_SK EE_DO EE_DI Pin B12 A12 C12 Signal EE_CS_N FLSH_SCK FLSH_CE_N Pin C13 R10 P10 Signal FLSH_SI FLSH_SO Pin T9 R9
Table 29. LED Signals
Signal LED0_0 LED0_2 LED0_3 Pin B11 B10 C10 Signal LED0_1 LED1_0/RSVD_P8 LED1_2/RSVD_T8 Pin C11 P8 T8 Signal LED1_3/RSVD_P9 LED1_1/RSVD_R8 Pin P9 R8
Table 30. Other Signals
Signal SDP0_0 SDP0_1 SDP0_2 SDP0_3 Pin B9 A9 C9 A8 Signal SDP1_0/RSVD_P6 SDP1_1/RSVD_B6 SDP1_2/RSVD_C6 SDP1_3/RSVD_R6 Pin P6 B6 C6 R6
Table 31. PHY and SERDES Signals
Signal MDI_MINUS0_0 MDI_PLUS0_0 MDI_MINUS0_1 MDI_PLUS0_1 MDI_MINUS0_2 MDI_PLUS0_2 MDI_MINUS0_3 MDI_PLUS1_2/ RSVD_P16
Pin B14 A14 B15 A15 C15 C16 D15 P16
Signal MDI_MINUS1_3/ RSVD_N15 MDI_PLUS1_3/ RSVD_N16 RBIAS0n RBIAS0p RBIAS1n/ RSVD_N14 RBIAS1p/ RSVD_M14 SRDSO_0_MINUS SRDSO_0_PLUS
Pin N15 N16 D14 E14 N14 M14 F15 G15
Signal SRDSI_0_MINUS SRDSI_0_PLUS SRDSO_1_MINUS/ RSVD_L15 SRDSO_1_PLUS/ RSVD_K15 SRDSB_SIG_DET/ RSVD_C4 SRDSI_1_MINUS/ RSVD_L16 SRDSI_1_PLUS/ RSVD_M16 SRDSA_SIG_DET
Pin F16 E16 L15 K15 C4 L16 M16 B4
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Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Signal MDI_PLUS0_3 MDI_PLUS1_1/ RSVD_T15 MDI_MINUS1_2/ RSVD_P15
Pin D16 T15 P15
Signal MDI_MINUS1_0/ RSVD_R14 MDI_PLUS1_0/ RSVD_T14 MDI_MINUS1_1/ RSVD_R15
Pin R14 T14 R15
Signal SRDS_RCOMPn SRDS_RCOMPp
Pin H14 H15
Table 32. Test Interface Signals
Signal JTCK JTDI JTDO JTMS TEST_EN Pin P4 R3 P5 P3 R5 Signal IEEE_TEST0n IEEE_TEST0p IEEE_TEST1n/ RSVD_T13 IEEE_TEST1p/ RSVD_R13 Pin A13 B13 T13 R13 Signal THERM_Dp THERM_Dn Pin D4 D5
Table 33. Crystal Signals
Signal XTAL1 XTAL2 Pin J16 H16
Product Datasheet
37
82571EB/82572EI Gigabit Ethernet Controller
Table 34. Power Signals
Signal VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC18 VCC18 VCC18 VCC18 VCC18 VCC18 VCC18 VCC18 VCC18 VCC18 VCC18 Pin A4 A10 D7 D9 N7 N9 T5 T11 E10 F10 G10 H10 J10 K10 L10 M10 H4 H5 K5 Signal VCC18 VCC18 VCC18 VCC11 VCC11 VCC11 VCC11 VCC11 VCC11 VCC11 VCC11 VCC11 VCC11 VCC11 VCC11 VCC11 VCC11 VCC11 VCC11 Pin M4 M5 K4 E7 E9 E13 F7 F9 G7 G9 H7 H9 J7 J9 K7 K9 L7 L9 M7 Signal VCC11 VCC11 VCC11 VCC11 VCC11 VCC11 VCC11 VCC11 VCC11 VCC11 VCC11 VCC11 VCC11 VCC11 Pin M9 M13 E12 F13 G12 K12 L13 M12 F12 L12 J4 J5 N4 N5
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Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Table 35. Ground Signals
Signal VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA Pin A1 A16 B16 C2 C14 D1 D3 D11 D12 D13 E3 E4 E11 E15 F2 F3 F4 F11 F14 G1 G3 G4 G5 G11 G13 G14 G16 H3 H11 H12 Signal VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA Pin H13 J3 J11 J12 J13 K1 K3 K11 K13 K14 K16 L2 L3 L4 L5 L11 L14 M3 M11 M15 N1 N3 N11 N12 N13 P2 P14 R16 T1 T16 Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin A5 A11 D6 D8 D10 E5 E6 E8 F5 F6 F8 G6 G8 H6 H8 J6 J8 K6 K8 L6 L8 M6 M8 N6 N8 N10 T4 T10
Product Datasheet
39
82571EB/82572EI Gigabit Ethernet Controller
Table 36. Reserved and No Connect Signals
Note: These pins are reserved by Intel and may have factory test functions. For normal operation, do not connect any circuitry to these pins (allow them to "float"). Some configurations may require pull-up or pull-down resistors on these pins. Please refer to the 82571EB/82572EI design guide for more information.
Signal RSVD_A3 RSVD_ A6 DEVICE_DIS_N RSVD_B3 RSVD_ B5 RSVD_ C3 RSVD_ C5 RSVD_ C7 RSVD_H1 RSVD_J1 RSVD_J14 RSVD_J15 LAN_PWR_GOOD NC_T7
Pin A3 A6 A7 B3 B5 C3 C5 C7 H1 J1 J14 J15 R4 T7
Table 37. Signal Names in Pin Order (Sheet 1 of 8)
Signal Name VSSA PETn3 RSVD_A3 VCC33 VSS RSVD_A6 DEVICE_DIS_N SDP0_3 SDP0_1 VCC33 VSS EE_DO IEEE_TEST0n MDI_PLUS0_0 MDI_PLUS0_1 VSSA Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
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Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Table 37. Signal Names in Pin Order (Sheet 2 of 8)
Signal Name PERn3 PETp3 RSVD_B3 SRDSA_SIG_DET RSVD_B5 SDP1_1/RSVD_B6 LAN0_DIS_N LAN1_DIS_N/RSVD_B8 SDP0_0 LED0_2 LED0_0 EE_SK IEEE_TEST0p MDI_MINUS0_0 MDI_MINUS0_1 VSSA PERp3 VSSA RSVD_C3 SRDSB_SIG_DET/RSVD_C4 RSVD_C5 SDP1_2/RSVD_C6 RSVD_C7 AUX_PWR SDP0_2 LED0_3 LED0_1 EE_DI EE_CS_N VSSA MDI_MINUS0_2 MDI_PLUS0_2 VSSA PETn2 VSSA THERM_Dp THERM_Dn VSS Pin B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6
Product Datasheet
41
82571EB/82572EI Gigabit Ethernet Controller
Table 37. Signal Names in Pin Order (Sheet 3 of 8)
Signal Name VCC33 VSS VCC33 VSS VSSA VSSA VSSA RBIAS0n MDI_MINUS0_3 MDI_PLUS0_3 PERn2 PETp2 VSSA VSSA VSS VSS VCC11 VSS VCC11 VCC18 VSSA VCC11 VCC11 RBIAS0p VSSA SRDSI_0_PLUS PERp2 VSSA VSSA VSSA VSS VSS VCC11 VSS VCC11 VCC18 VSSA VCC11 Pin D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12
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Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Table 37. Signal Names in Pin Order (Sheet 4 of 8)
Signal Name VCC11 VSSA SRDSO_0_MINUS SRDSI_0_MINUS VSSA PE_RCOMPn VSSA VSSA VSSA VSS VCC11 VSS VCC11 VCC18 VSSA VCC11 VSSA VSSA SRDSO_0_PLUS VSSA RSVD_H1 PE_RCOMPp VSSA VCC18 VCC18 VSS VCC11 VSS VCC11 VCC18 VSSA VSSA VSSA SRDS_RCOMPn SRDS_RCOMPp XTAL2 RSVD_J1 PE_CLKn Pin F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2
Product Datasheet
43
82571EB/82572EI Gigabit Ethernet Controller
Table 37. Signal Names in Pin Order (Sheet 5 of 8)
Signal Name VSSA VCC11 VCC11 VSS VCC11 VSS VCC11 VCC18 VSSA VSSA VSSA RSVD_J14 RSVD_J15 XTAL1 VSSA PE_CLKp VSSA VCC18 VCC18 VSS VCC11 VSS VCC11 VCC18 VSSA VCC11 VSSA VSSA SRDSO_1_PLUS/RSVD_K15 VSSA PETn1 VSSA VSSA VSSA VSSA VSS VCC11 VSS Pin J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8
44
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Table 37. Signal Names in Pin Order (Sheet 6 of 8)
Signal Name VCC11 VCC18 VSSA VCC11 VCC11 VSSA SRDSO_1_MINUS/RSVD_L15 SRDSI_1_MINUS/RSVD_L16 PETp1 PERn1 VSSA VCC18 VCC18 VSS VCC11 VSS VCC11 VCC18 VSSA VCC11 VCC11 RBIAS1p/RSVD_M14 VSSA SRDSI_1_PLUS/RSVD_M16 VSSA PERp1 VSSA VCC11 VCC11 VSS VCC33 VSS VCC33 VSS VSSA VSSA VSSA RBIAS1n/RSVD_N14 Pin L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14
Product Datasheet
45
82571EB/82572EI Gigabit Ethernet Controller
Table 37. Signal Names in Pin Order (Sheet 7 of 8)
Signal Name MDI_MINUS1_3/RSVD_N15 MDI_PLUS1_3/RSVD_N16 PETn0 VSSA JTMS JTCK JTDO SDP1_0/RSVD_P6 FLBSD LED1_0/RSVD_P8 LED1_3/RSVD_P9 FLSH_CE_N PE_WAKEn SMBD1 SMBCLK1 VSSA MDI_MINUS1_2/RSVD_P15 MDI_PLUS1_2/RSVD_P16 PETp0 PERn0 JTDI LAN_PWR_GOOD TEST_EN SDP1_3/RSVD_R6 FLBINTEX LED1_1/RSVD_R8 FLSH_SO FLSH_SCK SMBALRT_N/PCI_PWR_GOOD SMBD0/FLBMD IEEE_TEST1p/RSVD_R13 MDI_MINUS1_0/RSVD_R14 MDI_MINUS1_1/RSVD_R15 VSSA VSSA PERp0 DEV_OFF_N VSS Pin N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4
46
Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
Table 37. Signal Names in Pin Order (Sheet 8 of 8)
Signal Name VCC33 PE_RSTn NC_T7 LED1_2/RSVD_T8 FLSH_SI VSS VCC33 SMBCLK0/FLBMCK IEEE_TEST1n/RSVD_T13 MDI_PLUS1_0/RSVD_T14 MDI_PLUS1_1/RSVD_T15 VSSA Pin T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Product Datasheet
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82571EB/82572EI Gigabit Ethernet Controller
5.4
Visual Pin Assignments
A 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
VSSA
B
VSSA MDI_ MINUS0_1 MDI_MINUS0_0 IEEE_TEST0p EE_SK LED0_0 LED0_2 SDP0_0 LAN1_DIS_N/ RSVD_B8 LAN0_DIS_N SDP1_1/ RSVD_B6 RSVD_B5
C
MDI_ PLUS0_2 MDI_ MINUS0_2 VSSA EE_CS_N EE_DI LED0_1 LED0_3 SDP0_2
D
MDI_ PLUS0_3 MDI_ MINUS0_3 RBIAS0n VSSA VSSA VSSA VSS VCC33
E
SRDSI_0 _PLUS VSSA
F
SRDSI_0 _MINUS SRDSO_0 _MINUS VSSA VCC11 VCC11 VSSA VCC18 VCC11
G
VSSA SRDSO_0 _PLUS VSSA VSSA VCC11 VSSA VCC18 VCC11
H
XTAL2
MDI_PLUS0_1
SRDS_RCOMPp
MDI_PLUS0_0 IEEE_TEST0n EE_DO VSS VCC33 SDP0_1
RBIAS0p VCC11 VCC11 VSSA VCC18 VCC11
SRDS_RCOMPn VSSA VSSA VSSA VCC18 VCC11
SDP0_3
AUX_PWR
VSS
VSS
VSS
VSS
VSS
DEVICE_DIS_N
RSVD_C7 SDP1_2/ RSVD_C6 RSVD_C5 SRDSB_SIG_DET/ RSVD_C4 RSVD_C3 VSSA PERp3
VCC33
VCC11
VCC11
VCC11
VCC11
RSVD_A6
VSS THERM_ Dn THERM_ Dp VSSA PETn2 VSSA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA
VCC18
VCC33
SRDSA_SIG_DET
VSSA
VSSA
VSSA
VCC18
RSVD_A3 PETn3 VSSA
RSVD_B3 PETp3 PERn3
VSSA PETp2 PERn2
VSSA VSSA PERp2
VSSA PE_RCOMPn VSSA
VSSA PE_RCOMPp RSVD_H1
Figure 10. 82571EB/82572EI Visual Pin Assignment pt.1 (Top View)
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Product Datasheet
82571EB/82572EI Gigabit Ethernet Controller
J
XTAL1
K
VSSA SRDSO_1_ PLUS/RSVD_K15 VSSA
L
SRDSI_1_MINUS/ RSVD_L16 SRDSO_1_ MINUS/RSVD_L15 VSSA
M
SRDSI_1_PLUS/ RSVD_M16 VSSA RBIAS1p/ RSVD_M14 VCC11
N
MDI_PLUS1_3/ RSVD_N16 MDI_MINUS1_3/ RSVD_N15 RBIAS1n/ RSVD_N14 VSSA
P
MDI_PLUS1_2/ RSVD_P16 MDI_MINUS1_2 /RSVD_P15 VSSA
R
VSSA MDI_MINUS1_1/ RSVD_15 MDI_MINUS1_0/ RSVD_R14 IEEE_TEST1p/ RSVD_R13 SMBD0/FLBMD SMBALRT_N/ PCI_PWR_GOOD FLSH_SCK
T
VSSA MDI_PLUS1_1 /RSVD_T15 MDI_PLUS1_0 /RSVD_T14 IEEE_TEST1n/ RSVD_T13 SMBCLK0/ FLBMCK VCC33
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
RSVD_J15
RSVD_J14
VSSA
VSSA
VCC11
SMBCLK1
VSSA
VCC11
VCC11
VCC11
VSSA
SMBD1
VSSA
VSSA
VSSA
VSSA
VSSA
PE_WAKEn
VCC18
VCC18
VCC18
VCC18
VSS
FLSH_CE_N LED1_3/ RSVD_P9 LED1_0/ RSVD_P8 FLBSD SDP1_0/ RSVD_P6 JTDO JTCK JTMS VSSA PETn0
VSS
VCC11
VCC11
VCC11
VCC11
VCC33
FLSH_SO LED1_1/ RSVD_R8 FLBINTEX SDP1_3/ RSVD_R6 TEST_EN RSVD JTDI PERn0 PETp0
FLSH_SI LED1_2/ RSVD_T8 NC_T7
VSS
VSS
VSS
VSS
VSS
VCC11
VCC11
VCC11
VCC11
VCC33
VSS
VSS
VSS
VSS
VSS
PE_RSTn
VCC11 VCC11 VSSA PE_CLKn RSVD_J1
VCC18 VCC18 VSSA PE_CLKp VSSA
VSSA VSSA VSSA VSSA PETn1
VCC18 VCC18 VSSA PERn1 PETp1
VCC11 VCC11 VSSA PERp1 VSSA
VCC33 VSS DEV_OFF_N PERp0 VSSA
Figure 11. 82571EB/82572EI Visual Pin Assignment pt.2 (Top View)
Product Datasheet
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82571EB/82572EI Gigabit Ethernet Controller
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Product Datasheet

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